LIBRARY IEEE;             
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE WORK.TYPES.ALL;

entity EX_MEM is
    port(
        clock,reset     : IN  STD_LOGIC;

        --Sinais de passagem
        Regwrite_in     : IN  STD_LOGIC;
        MemtoReg_in     : IN  STD_LOGIC;
        MemRead_in      : IN  STD_LOGIC;
        MemWrite_in     : IN  STD_LOGIC;
        Branch_in       : IN  STD_LOGIC;
        read_data_2_in  : IN  MEMDATA;
        Regwrite_out    : OUT STD_LOGIC;
        MemtoReg_out    : OUT STD_LOGIC;
        MemRead_out     : OUT STD_LOGIC;
        MemWrite_out    : OUT STD_LOGIC;
        Branch_out      : OUT STD_LOGIC;
        read_data_2_out : OUT MEMDATA;

        --Endereço
        Add_result_in   : IN  MEMADDR;
        WrAddr_in       : IN  REGADDR;
        Add_result_out  : OUT MEMADDR;
        WrAddr_out      : OUT REGADDR;

        --ULA
        Zero_in         : IN  STD_LOGIC;
        ALU_result_in   : IN  MEMDATA;
        Zero_out        : OUT STD_LOGIC;
        ALU_result_out  : OUT MEMDATA
    );
end EX_MEM;

architecture pipe of EX_MEM is
begin
    process (clock)
    begin
        if rising_edge(clock) then
            --Passagem:
            Regwrite_out    <= Regwrite_in;
            MemtoReg_out    <= MemtoReg_in;
            MemRead_out     <= MemRead_in;
            MemWrite_out    <= MemWrite_in;
            Branch_out      <= Branch_in;
            read_data_2_out <= read_data_2_in;
            --Endereço:
            Add_result_out  <= Add_result_in;
            WrAddr_out      <= WrAddr_in;
            --ULA:
            Zero_out        <= Zero_in;
            ALU_result_out  <= ALU_result_in;
        end if;
    end process;
end pipe;

